This article mainly discusses how various defects in silicon wafers affect the performance of solar cells:
1. Impact of Silicon Ingot Grinding and Polishing on Solar Cell Performance
Silicon is a brittle material, and after cutting large polycrystalline ingots into smaller silicon ingots, the surface of the small ingots will have a damaged layer, which includes shattered grain regions, dislocation network areas, and elastic strain zones, as shown in Figure 1. The shattered grain area, also known as the micro-crack zone, is composed of broken silicon grains; the dislocation network area contains a large number of dislocations; and the elastic strain zone features elastic strain, causing the silicon atoms to be arranged irregularly.
Figure 1
Due to the presence of the damaged layer, particularly the micro-crack zone with numerous micro-cracks, it becomes easy for cracks to start during subsequent processes such as slicing, battery production, and module production. This leads to issues such as hidden cracks, micro-cracks, edge chipping, and debris in the wafers or solar cells.
Figure 2
Therefore, after cutting large polycrystalline ingots into smaller ingots, it is common practice to use mechanical grinding or chemical polishing to remove or reduce the damage layer on the surface of the ingot.
Figure3
For example, silicon wafers from a supplier that had not been mechanically ground or chemically polished had an average debris rate of about 1.5% during the battery line production. After mechanical grinding, the debris rate dropped to 0.7%, more than halving the debris rate.
2. Impact of Saw Marks, Steps, and Thickness Variations on Solar Cell Performance
Bulk experiments were conducted on wafers with defects such as saw marks, steps, and thickness variations. For instance, saw marks had a depth greater than 30 µm, steps ranged from 30-40 µm deep, and thickness variations ranged from 130-330 µm.
Due to local high and low elevations and thickness differences on the wafer, the debris rate increases during the manufacturing processes of the solar cells due to uneven stress. In the screen printing process, especially for saw-marked and stepped wafers with abrupt height changes, it is easy to cause electrode or backsheet printing defects, leading to poor quality electrodes.
As shown in Figures 3 and 4, the debris rate, electrode failure rate, and total scrap and defect rate for saw-marked, stepped, and thickness-uneven wafers are significantly higher than those for normal wafers. The total scrap and defect rate is 4%-10% higher than that of normal wafers.
Figure 3
Comparison of defect rates in battery production for various defective wafers
Figure 4
Comparison of defect rates in module production for various defective wafers
3. Impact of Surface Contamination on Solar Cell Performance
Figure 5
Fingerprints causing surface contamination of silicon wafers can lead to abnormalities during the texturing process.
Figure 6
Uncleaned silicon wafers with organic oil contamination or cleaning fluid residue cause surface contamination, leading to abnormalities during the texturing process.
Figure 7
If the surface of the silicon wafer is contaminated with oil or other substances, the pyramid structure on the surface may not form correctly after the texturing process.
Figure 8
Fingerprints or incorrect handling of the silicon wafer during the original processing can result in contamination that is not removed during the texturing process, leading to color spots in the PECVD (Plasma-Enhanced Chemical Vapor Deposition) process.
In conclusion, various defects in silicon wafers, including mechanical damage, surface contamination, and irregularities like saw marks and thickness variations, significantly affect the performance and yield of solar cells during production. Addressing these issues through careful wafer handling, polishing, and cleaning is critical for improving the efficiency and quality of solar cells.